Microcontroller Instruction Set. For interrupt response time information, refer to the hardware description chapter. Note: 1. Operations on SFR byte address. The instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal RAM to facilitate byte. Instructions. has about instructions. These can be grouped into the following categories. Arithmetic Instructions; Logical Instructions; Data.

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It features extended instructions [34] — see also the programmer’s guide [35] — and later variants with higher performance, [36] also sef as intellectual property IP.

Instruction Set

These registers also allowed the to quickly perform a context switch. Set when addition produces a carry from bit 3 to bit 4. The last digit can indicate memory size, e. Retrieved from ” https: This specifies the address of the next instruction to execute. This page was last edited on 1 Decemberat The AT89C51 provides the following.


Intel MCS – Wikipedia

JNB bitoffset jump if bit clear. The on-chip PEROM allows the program memory to be reprogrammedon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.

Intel discontinued its MCS product line in March ; [23] [24] however, there are plenty of enhanced products or silicon intellectual property added regularly from other vendors.

The mnemonics for Accumulator-specific instructionshowever, refer to the Accumulator simply as Adivide operations. The low-order bit of the register bank.

Although most instructions require that one operand is the accumulator or an immediate constant, it is possible to perform a MOV directly between two internal RAM locations.

There are many commercial C compilers.

ORL addressdata. Embedded system Programmable logic controller. Gives the parity XOR of the bits of the accumulator, A. ADD Adata.

Most clones also have a full bytes of IRAM. By using this site, you agree to the Terms of Use and Privacy Policy. Figure 1 shows a map of at899c51 AT89C51 program memorymemory expansion. MOV Adata.

Figure 1 shows a map of the AT89C51 program memory, and Figure 2.

8051 Instruction Set

In some engineering schools, the microcontroller is used in introductory microcontroller courses. Modern cores are faster than earlier packaged versions. ORL Cbit. This part was available in a ceramic package with a clear quartz window over the top of the die so UV light could be used to erase the EPROM memory.


ANL addressA. JB bitoffset jump if bit set. ADDC Adata. Retrieved 6 January The operations specified by the most significant nibble are as follows.

Intel MCS-51

One of the reasons for the ‘s instryction is its range of operations on single bits. External data memory XRAM is a third address space, also starting at address 0, and allowing 16 bits of address space. Register select 0, RS0. More than 20 independent manufacturers produce MCS compatible processors. CamelForth for the “.

There are various high-level programming language compilers for the